1. Field of the Invention
The invention relates to a wobble clock signal generating circuit of an optical disc drive, and more particularly, to a wobble clock signal generating circuit having both a controlling mechanism and the capability of generating a non-phase-modulated wobble clock signal according to a phase-modulated wobble signal.
2. Description of the Prior Art
In present day information society, storage of large amounts of information has become a major problem. Of all types of storage medium, the optical disc is one of the most useful mediums because of its high storage capacity and small physical volume. However, as multimedia technology progresses increased storage requirements are required, and the storing capacity of a normal CD optical disc (650 MB) is becoming increasingly less satisfactory. Therefore, a new optical disc standard, the digital versatile disc (DVD), with increased storage capacity, has emerged. The physical size of a DVD is almost identical to that of a CD; however, the storage capacity of a DVD is much larger than that of a CD. The DVD, also known as a multi-function digital disc, was first utilized for storing video data because of its large storing capacity (about 4.7 GB in a storing layer). A video approximately two hours in length can be stored on the storing layer. However, as the DVD becomes more popular, the multi-function digital disc is gradually being used for other storage tasks. For instance, large amounts of backed up data off a computer's hard drive can be often stored on a single multi-function digital disc, compared to the multiple number of CDs required to do the same task.
FIG. 1 is a diagram of a pickup head of an optical disc drive 31 in the process of reading data from an optical disc. The optical pickup head 31 comprises a receiver (not shown in FIG. 1) for reading data signals 30 on the data tracks, and four sensors Sa, Sb, Sc, Sd for reading the information of a wobble track 28 (or simply wobble). The wobble track is used predominantly for addressing the data signal on the DVD. In FIG. 1, the positions of Sa and Sd correspond to the troughs (or grooves) of the wobble track 28 on the reflection layer of the optical disc, and the positions of Sc and Sb correspond to the peaks (or bulges) of the wobble track 28 of the reflection layer of the optical disc. Because of the differences between reflection characteristics of the grooves and bulges, sensors Sa, Sb, Sc, Sd detect different amount of reflected light. The reflection amount detected by sensor Sa is subtracted by the reflection amount detected by sensor Sd, and the subtracted value is converted into an electric signal such that a wobble signal is generated. With the rotation of the optical disc, the optical pickup head 31 travels along the reflection layer in the direction of arrow 32 and receives reflection values from each sensor along the track. The sensors Sa–Sd installed on the top of the optical pickup head 31 detect different reflection values as they cross the curves of wobble track 28. For example, when the optical pickup head 31 reaches position P1, sensors Sa, Sd move from the groove to the bulge of the wobble track. Therefore, the optical pickup head 31 can generate a wobble signal due to the wobble track, and ADIP (Address In Pre-groove) can be read by decoding the wobble signal.
As known by those skilled in the art, ADIP are stored in the wobble track through phase modulation. Every two storage-areas of the optical disc 10 correspond to 93 wobbles, where 8 wobbles are used to store ADIP through phase modulation. Therefore, the optical disc drive has to utilize an ADIP decoder to get the ADIP from the wobble signal.
FIG. 2 is a diagram of a prior art analog ADIP decoder 40. The ADIP decoder 40 comprises a delay circuit 42, a mixer 44, a phase lock loop (PLL) 46, a frequency divider 48, and a XOR logic arithmetic circuit 50. The following trigonometric function is used as the foundation of the ADIP decoder:
                                          Sin            ⁡                          (              θ              )                                *                      Cos            ⁡                          (              θ              )                                      =                              1            2                    ⁢                                    Sin              ⁡                              (                                  2                  ⁢                                                                          ⁢                  θ                                )                                      .                                              (        1        )            
If the wobble signal is represented as Sin(θ), then 0.5*Sin(2θ) can be obtained from equation 1. As mentioned above, the ADIP are stored in the wobble signal through phase modulation, therefore, when the wobble signal, and the corresponding ADIP, have a 180-degrees phase shift, the wobble signal is represented as Sin(θ+180°). According to the above equation 1, 0.5*Sin(2θ+360°) can be calculated from Sin(θ+180°). Furthermore, 0.5*Sin(2θ+360°) is equal to 0.5*Sin(2θ), therefore, a non-phase-modulated wobble clock can be generated according to the phase-modulated wobble signal. The analog ADIP decoder 40 generates the non-phase-modulated wobble clock according to the above-mentioned concepts, and executes decoding operation for reading ADIP according to the wobble clock.
As shown in FIG. 2, signal S1 is a wobble signal, and the delay circuit 42 is used to delay signal S1 for generating signal S2. The delay circuit 42 delays signal S one quarter of a period. This means that the phase difference between signal S2 and signal S1 is 90° such that if signal S1 is represented by Sin(θ), signal S2 is represented by Sin(θ+90°) or Cos(θ). The mixer 44 is used to multiply signals S1 and S2 together to generate signal S3. According to equation 1, signal S3 is 0.5*Sin(2θ), thus the frequency of signal S3 is double of that of signal S1. Then using signal S3, the PLL 46 generates signal S4 that is synchronous to signal S3. This means that the PLL 46 outputs a signal S4 equal to Sin(2θ). Finally, the frequency divider 48 divides signal S4, and generates signal S5 that has half of the frequency of signal S4. Note that signal S5 is a non-phase-modulated wobble clock signal (wobble clock hereafter), and signal S1 is a phase-modulated wobble signal. Therefore, after the XOR logic arithmetic circuit 50 executes an XOR logic arithmetic on signal S5 and signal S1, the ADIP can be obtained from the period of phase change of signal S1 obtained by the above-mentioned operations.
Because the analog circuit cannot accurately differentiate signal S1 to generate signal S2, the delay circuit 42 is used to change signal from Sin(θ) to Cos(θ). This means that the delay circuit 42 has to delay signal S1 one quarter of a period. But if rotating speed of the optical disc varies, the frequency of signal S1 also changes. So the delay circuit 42 needs to be self-adjusting in order to provide an accurate delay based on the varying signal S1. This in particular, makes the delay circuit 42 complicated and difficult to design and produce.
FIG. 3 is a diagram of a prior art digital ADIP decoder 60. The digital ADIP decoder 60 comprises an analog-to-digital converter (ADC) 62, a differentiator 64, a multiplier 66, PLL 68, a frequency divider 70, and an XOR logic arithmetic circuit 72. The digital ADIP decoder 60 also generates a non-phase-modulated wobble clock for executing decoding operation on the wobble signal according to the above-mentioned equation 1. Signal S1 is an analog wobble signal, therefore the ADC 62 transforms the analog signal S1 into a corresponding digital signal S2 for further digital signal processing. The differentiator 64 differentiates signal S2 to generate a corresponding signal S3. If the analog signal S1 is Sin(θ), then the digital signal S2 can still be regarded as Sin(θ). After the differentiation operation, signal S3 is equal to Cos(θ). The multiplier 66 is used to execute multiplying operation on Signals S2 and S3 to output signal S4. According to equation 1, signal S4 is equal to 0.5*Sin(2θ). This means that the frequency of signal S4 is double of the frequency of signal S2.
Then signal S4 is fed into the PLL 68 generating a clock signal S5, which is fed back into the PLL 68 in order to ensure it is synchronous to signal S4. This means that the PLL 68 can output signal S5 corresponding to Sin(2θ). Next, the frequency divider 70 divides signal S5, creating signal S6 that has half the frequency of signal S5. Finally, the XOR logic arithmetic circuit 72 executes an XOR logic arithmetic operation on signals S6 and S2. Thus, the period of phase variation of signal S2 is decoded, and the ADIP is obtained. Because the digital ADIP decoder 60 uses a differentiator 64 (versus a delay circuit) to generate the Cos(θ) signal, the self-adjusting delay problem of the analog decoder 40 is circumvented.
When the digital ADIP decoder 60 operates, the analog wobble signal is first digitalized and then differentiated. Success of this device is dependent upon the high execution efficiency of the ADC 62 and the differentiator 64. Furthermore, to prevent distortion while transforming the analog signal S1 into the digital signal S2, the ADC 62 must use many bits to quantify the analog signal. These two points in particular, drive the cost of the digital ADIP decoder 60 up, such that the markets of high-speed DVD+R and DVD+RW optical disc drives, do not bear the cost thought the advantage is high.]